Voltage-controlled MRAM for 3D Stackable Non-Volatile Memories
by Richard Dorrance, Juan G. Alzate, Sergiy S. Cherepov, Pramey Upadhyaya, Kang L. Wang, Pedram Khalili Amiri, Dejan Marković
Abstract:
This research introduces a voltage-controlled magnetoelectric random access memory (MeRAM) cell that (1) eliminates the need for CMOS access transistors; (2) achieves a $4F^2$ cell size, with the potential for sub-$1F^2$ effective cell sizes; (3) exhibits sub-10ns switching times for voltage pulses  1V; and (4) switching energies 100x lower than STT-RAMs. The memory cell uses an MTJ, with a voltage-controlled magnetic anisotropy (VCMA) switching mechanism, and a diode arranged into a crossbar array. Voltage pulses of the same polarity, but different amplitudes, are used to switch the MTJ device between the P and AP states. Voltage pulses of the opposite polarity will not switch the device, but rather reinforce the initial state. No external magnetic field is required. A small crossbar memory array is constructed from 65nm MTJs fabricated on a silicon wafer and discrete germanium diodes (Vth = 0.2V). Measured results show switching speeds below 10ns for voltage pulses  1V, with a thermal stability projected to greater than 10 years. Simulation results also show 100x lower switching energies than STT-RAMs in a 22nm technology node.
Reference:
R. Dorrance, J. G. Alzate, S. S. Cherepov, P. Upadhyaya, K. L. Wang, P. K. Amiri, D. Marković, "Voltage-controlled MRAM for 3D Stackable Non-Volatile Memories," in Proceedings of the International Solid-State Circuits Conference Student Research Preview (ISSCC'13), February 2013.
Bibtex Entry:
@INPROCEEDINGS{Dorrance2013:ISSCC,
    author    = {Dorrance, Richard and Alzate, Juan G. and Cherepov, Sergiy S. and Upadhyaya, Pramey and Wang, Kang L. and Amiri, Pedram Khalili and Markovi\'{c}, Dejan},
    title     = {{Voltage-controlled MRAM for 3D Stackable Non-Volatile Memories}},
    booktitle = {Proceedings of the International Solid-State Circuits Conference Student Research Preview (ISSCC'13)},
    year      = {2013},
    month     = {February},
    doi       = {10.1109/ISSCC.2013.6487596},
    abstract  = {This research introduces a voltage-controlled magnetoelectric random access memory (MeRAM) cell that (1) eliminates the need for CMOS access transistors; (2) achieves a $4F^{2}$ cell size, with the potential for sub-$1F^{2}$ effective cell sizes; (3) exhibits sub-10ns switching times for voltage pulses ~1V; and (4) switching energies 100x lower than STT-RAMs. The memory cell uses an MTJ, with a voltage-controlled magnetic anisotropy (VCMA) switching mechanism, and a diode arranged into a crossbar array. Voltage pulses of the same polarity, but different amplitudes, are used to switch the MTJ device between the P and AP states. Voltage pulses of the opposite polarity will not switch the device, but rather reinforce the initial state. No external magnetic field is required. A small crossbar memory array is constructed from 65nm MTJs fabricated on a silicon wafer and discrete germanium diodes (Vth = 0.2V).  Measured results show switching speeds below 10ns for voltage pulses ~1V, with a thermal stability projected to greater than 10 years. Simulation results also show 100x lower switching energies than STT-RAMs in a 22nm technology node.},
    url       = {http://rdorrance.bol.ucla.edu/pdf/Voltage-controlled%20MRAM%20for%203D%20Stackable%20Non-Volatile%20Memories.pdf}
}
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