A Scalable Sparse Matrix-Vector Multiplication (SpMxV) Kernel For Sparse-BLAS on FPGAs
by Richard Dorrance, Fengbo Ren, Dejan Marković
Abstract:
Sparse Matrix-Vector Multiplication (SpMxV) is a widely used mathematical operation in many high-performance scientific and engineering applications. In recent years, tuned software libraries for multi-core microprocessors (CPUs) and graphics processing units (GPUs) have become the status quo for computing SpMxV. However, the computational throughput of these libraries for sparse matrices tends to be significantly lower than that of dense matrices, mostly due to the fact that the compression formats required to efficiently store sparse matrices mismatches traditional computing architectures. This paper describes an FPGA-based SpMxV kernel that is scalable to efficiently utilize the available memory bandwidth and computing resources. Benchmarking on a Virtex-5 SX95T FPGA demonstrates an average computational efficiency of 91.85%. The kernel achieves a peak computational efficiency of 99.8%, a >50x improvement over two Intel Core i7 processors (i7-2600 and i7-4770) and showing a >300x improvement over two NVIDA GPUs (GTX 660 and GTX Titan), when running the MKL and cuSPARSE sparse-BLAS libraries, respectively. In addition, the SpMxV FPGA kernel is able to achieve higher performance than its CPU and GPU counterparts, while using only 64 single-precision processing elements, with an overall 38-50x improvement in energy efficiency.
Reference:
R. Dorrance, F. Ren, and D. Marković, "A Scalable Sparse Matrix-Vector Multiplication (SpMxV) Kernel For Sparse-BLAS on FPGAs," in Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays (FPGA'14), pp. 161-170, February 2014.
Bibtex Entry:
@INPROCEEDINGS{Dorrance2014:FPGA,
    author    = {Dorrance, Richard and Ren, Fengbo and Markovi\'{c}, Dejan},
    title     = {{A Scalable Sparse Matrix-Vector Multiplication (SpMxV) Kernel For Sparse-BLAS on FPGAs}},
    booktitle = {Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays (FPGA'14)},
    year      = {2014},
    month     = {February},
    pages     = {161--170},
    doi       = {10.1145/2554688.2554785},
    abstract  = {Sparse Matrix-Vector Multiplication (SpMxV) is a widely used mathematical operation in many high-performance scientific and engineering applications. In recent years, tuned software libraries for multi-core microprocessors (CPUs) and graphics processing units (GPUs) have become the status quo for computing SpMxV. However, the computational throughput of these libraries for sparse matrices tends to be significantly lower than that of dense matrices, mostly due to the fact that the compression formats required to efficiently store sparse matrices mismatches traditional computing architectures. This paper describes an FPGA-based SpMxV kernel that is scalable to efficiently utilize the available memory bandwidth and computing resources. Benchmarking on a Virtex-5 SX95T FPGA demonstrates an average computational efficiency of 91.85%. The kernel achieves a peak computational efficiency of 99.8%, a >50x improvement over two Intel Core i7 processors (i7-2600 and i7-4770) and showing a >300x improvement over two NVIDA GPUs (GTX 660 and GTX Titan), when running the MKL and cuSPARSE sparse-BLAS libraries, respectively. In addition, the SpMxV FPGA kernel is able to achieve higher performance than its CPU and GPU counterparts, while using only 64 single-precision processing elements, with an overall 38-50x improvement in energy efficiency.},
    url       = {http://rdorrance.bol.ucla.edu/pdf/A%20Scalable%20Sparse%20Matrix-Vector%20Multiplication%20(SpMxV)%20Kernel%20For%20Sparse-BLAS%20on%20FPGAs.pdf}
}
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