Sort by: Type Year
2015
[J5] 
H. Lee, R. Dorrance, S. BasirKazeruni, D. Marković, P. K. Amiri, K. L. Wang, "A Spinbased Artificial Neuron for UltraScale Neuromorphic Computing," IEEE Transactions on Nanotechnology (TNANO), 2015.
[bibtex]

[J4] 
R. Dorrance and D. Marković, "Scalable Sparse Linear Algebra Kernel for Accelerating Bioinformatics on FPGAs," IEEE/ACM Transactions on Computational Biology and Bioinformatics (CBB), 2015.
[bibtex]

2014
[P3] 
P. K. Amiri, R. Dorrance, H. Lee, S. BasirKazeruni, D. Marković, K. L. Wang, "An Artificial Neuron based on the Spin Hall Effect," US Patent, University of California Case No. 2014???1, November 2014.
[bibtex]

[P2] 
P. K. Amiri, R. Dorrance, D. Marković, K. L. Wang, "ReadDisturbanceFree Nonvolatile Content Addressable Memory (CAM)," US Patent, US 20140071728 A1, March 2014.
[bibtex]
[pdf]
[google patents]

[P1] 
P. K. Amiri, R. Dorrance, D. Marković, K. L. Wang, "Nonvolatile MagnetoElectric Random Access Memory Circuit with Burst Writing and BacktoBack Reads," US Patent, US 20140071732 A1, March 2014.
[bibtex]
[pdf]
[google patents]

[C7] 
R. Dorrance, F. Ren, and D. Marković, "A Scalable Sparse MatrixVector Multiplication (SpMxV) Kernel For SparseBLAS on FPGAs," in Proceedings of the 2014 ACM/SIGDA International Symposium on Fieldprogrammable Gate Arrays (FPGA'14), pp. 161170, February 2014.
[bibtex]
[pdf]
[doi]

[J3] 
H. Lee, J. G. Alzate, R. Dorrance, D. Marković, P. K. Amiri, K. L. Wang, "Design of a Fast and LowPower Sense Amplifier and Writing Circuit for HighSpeed MRAM," IEEE Transactions on Magnetics (TMAG), vol. PP, pp. 11, 2014.
[bibtex]
[pdf]
[doi]

2013
[C6] 
F. Ren, R. Dorrance, W. Xu, D. Marković, "A SinglePrecision Compressive Sensing Signal Reconstruction Engine on FPGAs," in 2013 23rd International Conference on Field Programmable Logic and Applications (FPL'13), pp. 14, September 2013.
[bibtex]
[pdf]
[doi]

[J2] 
R. Dorrance, J. G. Alzate, S. S. Cherepov, P. Upadhyaya, I. Krivorotov, J. A. Katine, J. Langer, K. L. Wang, P. K. Amiri, D. Marković, "DiodeMTJ Crossbar Memory Cell Using VoltageInduced Unipolar Switching for HighDensity MRAM," IEEE Electron Device Letters (EDL), vol. 34, no. 6, pp. 753755, June 2013.
[bibtex]
[pdf]
[doi]

[C5] 
R. Dorrance, J. G. Alzate, S. S. Cherepov, P. Upadhyaya, K. L. Wang, P. K. Amiri, D. Marković, "Voltagecontrolled MRAM for 3D Stackable NonVolatile Memories," in Proceedings of the International SolidState Circuits Conference Student Research Preview (ISSCC'13), February 2013.
[bibtex]
[pdf]
[doi]

2012
[C4] 
J. G. Alzate, P. K. Amiri, P. Upadhyaya, S. S. Cherepov, J. Zhu, M. Lewis, R. Dorrance, J. A. Katine, J. Langer, K. Galatsis, D. Marković, I. Krivorotov, K. L. Wang, "VoltageInduced Switching of Nanoscale Magnetic Tunnel Junctions," in Proceedings of the International Electron Devices Meeting (IEDM'12), pp. 29.5.129.5.4, December 2012.
[bibtex]
[pdf]
[doi]

[J1] 
R. Dorrance, F. Ren, Y. Toriyama, A. A. Hafez, C. K. Yang, D. Marković, "Scalability and DesignSpace Analysis of a 1T1MTJ Memory Cell for STTRAMs," IEEE Transactions on Electron Devices (TED), vol. 59, no. 4, pp. 878887, April 2012.
[bibtex]
[pdf]
[doi]

[C3] 
F. Ren, H. Park, R. Dorrance, Y. Toriyama, C. K. Yang, D. Marković, "A BodyVoltageSensingBased Short Pulse Reading Circuit for SpinTorque Transfer RAMs (STTRAMs)," in Proceedings of 13th International Symposium on Quality Electronic Design (ISQED'12), pp. 275282, March 2012.
[bibtex]
[pdf]
[doi]

2011
[MS1] 
R. Dorrance, "Modeling and Design of STTMRAMs," Master's thesis, University of California, Los Angeles, June 2011.
[bibtex]
[pdf]

[C2] 
R. Dorrance, F. Ren, Y. Toriyama, A. A. Hafez, C. K. Yang, D. Marković, "Scalability and DesignSpace Analysis of a 1T1MTJ Memory Cell," in Proceedings of the ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH'11), pp. 3236, June 2011.
[bibtex]
[pdf]
[doi]

[C1] 
H. Park, R. Dorrance, A. A. Hafez, F. Ren, D. Marković, C. K. Yang, "Analysis of STTRAM Cell Design with Multiple MJTs Per Access," in Proceedings of the ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH'11), pp. 5358, June 2011.
[bibtex]
[pdf]
[doi]

Last updated: January 29, 2015